1. Field of the Invention
This invention relates to a semiconductor integrated microelectronic circuit device having a silicon-on-insulator (SOI) structure.
2. Description of the Related Art
SOI (silicon-on-insulator) technology is the fabrication of integrated semiconductor microelectronics circuitry on a three-layer substrate consisting of an upper layer of monocrystalline silicon, a layer of insulating material, usually an oxide of silicon, and an underlying layer of monocrystalline silicon. Although there are several methods for forming the SOI structure, wafer bonding or the SIMOX (separation by implanted oxygen) technique, which forms a buried oxide layer by driving oxygen ions into the silicon substrate, is commonly used. The circuitry is then primarily fabricated in the upper silicon layer, wherein it is substantially electrically isolated from the underlying silicon layer. SOI technology has become important precisely because it has the virtue of providing such degrees of isolation between circuit elements.
The very isolation of the thin upper silicon layer from the more substantial lower layer presents the possibility of unwanted surge currents in signal input lines, such as those caused by electrostatic discharges and the like, damaging circuit elements. One accepted way of ameliorating the effects of such currents is to provide the input line with a protective diode circuit to channel current surges away from the affected regions. Tsuruta et al. (U.S. Pat. No. 5,567,968) teach the formation of a protective diode structure that allows the passage of high currents in MOSFET circuitry fabricated in SOI layers. They teach a particular diode structure wherein a p-type semiconductor layer and an n-type semiconductor layer are electrically connected by a buried semiconductor layer to form a vertically disposed pn-junction. The diode so formed is then itself connected electrically to an adjacent MOSFET and thereby functions as an electrostatic discharge protection element. Suzuki et al. (U.S. Pat. No. 5,751,041) teach a method of protecting a CMOS inverter circuit formed in an SOI substrate by use of an np-diode connected between the signal input line and ground. They teach the formation of a second diffusion layer of a conductivity type that is the same as but of a higher concentration than that of the substrate, so as to circumscribe the extent of the depletion region and eliminate unwanted leakage currents. Fukumoto et al. (U.S. Pat. No. 5,786,616) teach the formation of a diode type circuit that protects against two types of surges: a surge between the signal input terminal and a ground terminal, and a surge between a signal input terminal and a power supply terminal, with the latter surge protection being the novel element of the invention. According to the method taught by Fukumoto et al., the power supply to signal input surges are protected against by a parasitic diode element formed between a resistor diffusion region and the underlying semiconductor substrate.
As can be seen from the above, the use of diode circuitry of one form or another to protect integrated SOI microelectronic circuits is an accepted part of the present art of fabricating such circuitry. Such protection, however, is not only needed when the SOI circuits are in actual use, it is also needed to protect the SOI circuitry from hazards that arise during its fabrication. In particular, the extensive use of plasmas in such fabrication processes as plasma assisted film depositions and etching causes the accumulation of charge deposits on conductive surfaces. If these charge excesses were not removed, they would produce potential differences across gate oxides which would be sufficient to cause their breakdown and damage or destroy transistors.
Another cause of circuit damage during SOI microelectronics fabrications as well as loss of circuit reliability is excessive heat buildup due to poor heat conduction and dissipation. The reduced size of modern microelectronic circuitry requires the use of low-k (low dielectric constant) materials to serve as interlayer dielectrics and insulating layers. Low-k materials, such as CORAL, manufactured by Novellus Corp., Black Diamond, manufactured by Applied Materials Corp., organic films from the Schumacher Corp. and various carbon-containing films, allow the formation of closely packed circuit elements without the attendant inter-element parasitic capacitances that would be associated with other dielectric materials. Unfortunately, such low-k dielectric materials also have low thermal conductivities, typically 0.24-0.37 W/k.m vs. 1.2 W/k.m for SiO2, which allows localized heat buildup in the fabrication. None of the methods discussed above address the problem of heat buildup or its reduction. The present invention addresses the heat dissipation problem simultaneously with the excess charge reduction problem by teaching a method of forming a PID protective diode that produces a structure capable of eliminating or significantly reducing both problems and does so efficiently, cost-effectively and in a manner that smoothly integrates its formation into the overall circuit fabrication scheme.
is an object of the present invention to teach a method of forming a xe2x80x9cplasma-induced-damagexe2x80x9d (PID) diode protective circuit for an SOI integrated microelectronic fabrication, such as a fabrication containing an arbitrary array of conductively interconnected nMOS and pMOS transistors disposed in single or multiple levels of integration.
It is yet another object of the present invention to teach a method of fabricating a PID diode protective circuit for an SOI integrated microelectronics fabrication that enhances the dissipation of heat produced during fabrication processes.
It is yet a further object of the present invention to teach a PID protective diode circuit fabrication method that is accomplished efficiently, cost-effectively and in a manner that smoothly integrates the diode formation into the overall fabrication scheme.
The objects of the present invention are achieved by a novel PID protective diode structure that conducts excess charge away from active portions of circuitry formed in the upper silicon layer of the SOI substrate, through a low resistance diode circuit, to the lowest silicon layer of the SOI substrate and, at the same time, conducts excess heat away from said portions of the circuitry, similarly conveying such heat to the lower silicon layer of the SOI substrate wherein it can be dissipated without damage to the fabricated circuitry. This is achieved by conductively connecting said diode to metal layers and structures, formed in various shapes over the various levels containing active portions of the circuitry, said layers and structures serving both as charge collectors and heat sinks and, thereby, conveying both charge and heat, through inter-level vias, directly to the lowest silicon layer of the SOI substrate.
The objects of the present invention are further achieved efficiently and cost-effectively by making use of an alignment opening formed during the fabrication process through which to form the diode in the lowest silicon layer of the SOI substrate.